1. Field of the Invention
This invention relates to an error correcting device performing error correction for data composed as an error correction data and a data reproducing device reading out data recorded in a recording medium such as a compact disc (CD) or a digital versatile disc (DVD).
2. Description of the Prior Art
First Prior Art
FIG. 39 illustrates a conventional error correcting device for use in a disc reproducing device for reproducing data recorded in a recording medium such as a DVD. The reproducing device comprises a receiving circuit 1 receiving data read from a disc by an optical pickup and composed as an error correcting code. Neither disc nor pickup is shown. The receiving circuit 1 then decodes the received data and then writes the decoded data through an arbitrator 2 into a storage device 3 such as a RAM. The data received by the receiving circuit 1 sometimes contains an error when the surface of the disc is damaged or dirty due to adherence of dirt such as fingerprints. In such a case, an error correcting circuit 4 reads out the data the receiving circuit 1 has written into the storage device 3 to thereby detect an error in the data. When detecting a correctable error, the error correcting circuit 4 corrects the data containing the error, writing the corrected data through the arbitrator 2 into the storage device 3.
The conventional error correcting device further comprises a transmission circuit 5 reading out the data having been corrected by the error correcting circuit 4 through the arbitrator 2 from the storage device 3. The transmission circuit 5 then transmits the read data to a reproduction system (not shown) for reproduction of the data as image or sound. The arbitrator 2 serves as a memory interface for arbitrating access of the receiving circuit 1, the error correcting circuit 4 and the transmission circuit 5 to the storage device 3.
FIG. 40 shows a concept of storage area of the storage device 3. The storage area of the storage device 3 is divided into three areas A, B and C. Each area has a storage capacity set to be equal to that of one block which is a unit for which the error correction is performed with use of the error correcting code. For example, as shown in FIG. 41, when the data received by the receiving circuit 1 is to be written into the area A in a phase, the data the receiving circuit 1 has written into the area C in the last phase is an object for error detection and correction, whereas the data which is stored in the area B and the error of which has been corrected by the error correcting circuit 4 in the last phase is an object to be transmitted by the transmission circuit 5.
In a next phase, the received data is to be stored in the area B, the error detection and correction are to be performed for the data stored in the area A, and the data stored in the area C is to be transmitted. Thus, the three areas are sequentially switched among three processes of data reception, error detection and correction, and data transmission. In this case, the receiving circuit 1 delivers both to the error correcting circuit 4 and to the transmission circuit 5 a status signal indicative of completion of reception of one block of data. Each of these circuits 4 and 5 confirms receipt of the status signal before performing the process for a new area.
According to the above-described system, the processes of data reception, error correction and data transmission can concurrently be executed in a time sharing. Accordingly, an operating speed of each circuit need not be increased to a large value. However, the storage device 3 requires a storage capacity at least three times larger than the one corresponding to one block of data. This results in a problem that a circuit is rendered large-sized.
In order to solve the above-mentioned problem, the inventors proposed an arrangement shown in FIG. 42. Specifically, a storage device with a storage capacity twice as large as the data block capacity (only areas A and B) is used instead of the storage device 3. While the receiving circuit 1 is writing data into either one of the areas A and B, the error correcting circuit 4 perform an error correction for the data stored in the other area and thereafter, the transmission circuit 5 transmits the error-corrected data. The two areas are thus switched therebetween.
According to the proposed system described above, the storage capacity of the storage device can be reduced. However, the error correction for one block of data by the error correcting circuit 4 and the transmission of the corrected data by the transmission circuit 5 need to be serially executed and completed within a time of write of another block of data into one of the areas by the receiving circuit 1. In this arrangement, accordingly, operating speeds of the error correcting circuit 4 and the transmission circuit 5 need to be increased. This results in a problem that the conditions of design of circuits including the circuits 4 and 5 is rendered more rigorous.
Second Prior Art
The inventors proposed an arrangement as shown in FIG. 43 as an error correcting device for use in a disc reproducing device for reproducing data stored in the CD or the DVD. In this arrangement, the receiving circuit 6 receives data read from a disc by an optical pickup and composed as an error correcting code, decoding the received data. Neither disc nor pickup is shown. The receiving circuit 1 then writes the decoded data through an arbitrator 7 into a storage device 8 such as a RAM.
An error correcting circuit 9 reads out the data the receiving circuit 6 has written into the storage device 8 to thereby detect an error in the data. When detecting a correctable error, the error correcting circuit 9 corrects the data containing the error, writing the corrected data through the arbitrator 7 into the storage device 8.
A transmission circuit 10 reads out the corrected data through the arbitrator 7 from the storage device 8. The transmission circuit 10 then transmits the read data to a reproduction system (not shown) for reproduction of the data as image or sound. The arbitrator 7 serves as a memory interface for arbitrating access of the receiving circuit 6, the error correcting circuit 9 and the transmission circuit 10 to the storage device 8. A syndrome calculating circuit 11 obtains data directly from the receiving circuit 6 to calculate syndrome from the error correcting code, delivering the result of calculation to the error correcting circuit 9.
For example, a DVD employs, as the error correcting code, a Reed-Solomon product code constituted by two sequences of error correcting codes comprising an inner parity (PI) code and an outer parity (PO) code. Accordingly, the receiving circuit 6 writes data of one block of product code into the storage device 8 and thereafter, the error correcting circuit 9 reads out the stored data from the storage device 8 to perform the error correction. Now assume an arrangement as shown in FIG. 43. In this arrangement, the syndrome calculating circuit 11 calculates syndrome concerning, for example, rows of PI code, so that the error correcting circuit 9 can start detection of error concerning a first row of PI code before the receiving circuit 6 finishes writing one block of product codes into the storage device 8. Consequently, a time required for the error detection and correction can be reduced.
However, in the above-described system, when disturbance occurring in a receiving system at the receiving circuit 6 side interrupts data reception, the syndrome calculating circuit 11 cannot obtain the number of units of information symbols required for the calculation of syndrome, resulting in a problem that the calculation of syndrome cannot properly be performed.
Further, the storage device 8 retains data written thereinto in the past and being currently meaningless due to interruption of data reception. In this regard, if the result of syndrome calculation concerning the meaningless data shows an error-correctable value, the error correcting circuit 9 disadvantageously corrects the meaningless data or performs a false correction. Upon occurrence of such a false correction, there is a possibility that an offensive noise is produced during sound reproduction, for example, when the data is sound data. Further, in a case where the data is file data, the contents of the file are sometimes broken or the data is erroneous when the file is opened to be displayed on a display, although it had properly been loaded. These phenomena are regarded as having an obscure causal relation by the user, resulting in a problem that the phenomena reduce the reliability of a product.
Third Prior Art
FIG. 44 illustrates further another conventional error correcting device for use in a disc reproducing device for reproducing data stored in a storage medium such as CD or DVD. FIG. 45 is a flowchart showing a sequence of processes carried out by components of the error correcting device as will hereinafter be described. A receiving circuit 12 receives and decodes data read from a disc by an optical pickup (neither shown) and composed as an error correcting code (step S1). The receiving circuit 12 writes the decoded data via an arbitrator 13 into a storage device such as a RAM (step S2).
An error correcting circuit 15 reads out the data written into the storage device 14 by the receiving circuit 12 (step S3), detecting an error in the data. When detecting a correctable error, the error correcting circuit 15 corrects the data containing the error. The error correcting circuit 15 writes the corrected data via the arbitrator 13 into the storage device 14 (step S4).
A transmission circuit 16 reads out the data corrected by the error correcting circuit 15 via the arbitrator 13 from the storage device 14 (step S5), transmitting the read data to a reproduction system (not shown) for reproduction of the data as image or sound (step S6). Further, an overwrite circuit 17 overwrites any data via the arbitrator 13 onto the data stored in the storage device 14 immediately after the data read from the storage device 14 has been transmitted by the transmission circuit 16, so that the error correcting circuit is rendered incapable of correcting error (step 57). As a result, the data having been transmitted is rewritten.
The overwriting operation of the overwrite circuit 17 is performed so that the error correcting circuit 15 is prevented from a false detection or a false correction by overwriting the unrenewed data previously written onto the storage device 14 for corrupting the data even when data cannot be written onto the storage device 14 due to disturbance in the data receiving conditions of the receiving circuit 12. The arbitrator 13 serves as a memory interface for arbitrating access of the receiving circuit 12, the error correcting circuit 15, the transmission circuit 16 and the overwrite circuit 17 to the storage device 14.
The number of times of access to the storage device 14 is increased in the above-described system wherein the data overwrite circuit 17 is provided for overwriting the transmitted data. Accordingly, a problem arises that a data transfer rate to the storage device 14 needs to be increased so that a processing speed required for the sequence of processes comprising data reception, error correction and data transmission is maintained at a predetermined level.
Fourth Prior Art
FIG. 46 illustrates further another conventional error detection device for use in a disc reproducing device for reproducing data stored in a storage medium such as CD or DVD. An RF (high frequency) circuit 18 receives data read out from a disc 19 by an optical pickup 20 and constituted as an error correcting code to equalize signal waveforms of the data to thereby deliver the equalized signal waveforms to a synchronization separating circuit 21, a PLL circuit 22 and a servo circuit 23.
The PLL circuit 22 produces reproduction clock signals based on the data signal waveforms, delivering the signals to the synchronization separating circuit 21 and a decoding circuit 24. The synchronization separating circuit 21 separates synchronization signals from the data signals based on the reproduction clock signals, delivering the synchronization signals to the decoding circuit 24. The decoding circuit 24 decodes the data from the supplied data signals, writing the decoded data via an arbitrator 25 onto a storage device comprising a RAM or the like.
An error correcting circuit 27 reads out the data written onto the storage device 26 by the decoding circuit 24 to detect error in the data. When detecting a correctable error, the error correcting circuit 27 corrects the data containing the error and thereafter writes the corrected data via the arbitrator 25 onto the storage device 26.
A transmission circuit 28 reads out the data corrected by the error correcting circuit 27 from the storage device 26 to transmit the data to a processing system (not shown) for reproducing the data as image or sound according to a type of the disc 19. The arbitrator 25 serves as a memory interface for arbitrating access of the decoding circuit 24, the error correcting circuit 27 and the transmission circuit 28 to the storage device 26.
The servo circuit 23 controls a motor 30 for turning the disc 19 and the pickup 20. Processes performed by the servo circuit 23, the error correcting circuit 27 and the transmission circuit 28 are based on clock signals supplied from a system reference clock circuit 31 to them. The servo circuit 23 is also supplied with a reproduction speed control signal from a system controller (not shown) according to input by a user.
An information storage system for the disc 19 at the above-described reproduction system includes a constant linear velocity (CLV) system wherein a linear velocity is constant, and a zone constant velocity (ZCLV) system wherein an angular velocity between zones is constant. The disc reproducing device reads out the data to reproduce image or sound according to the above-described or other reproduction systems. For example, in the CLV system, the servo circuit 23 controls the motor 30 and the pickup 20 as shown in FIG. 47, so that the disc 19 is rotated at a constant linear velocity. The servo circuit 23 further moves the pickup 20 from an inner circumferential side of the disc 19 to an outer circumferential side thereof by linear tracking, thereby reading data recorded on the disc 19 and writing it onto the storage device 26 in the same manner as described above. Thus, time variations in data readout by the motor 30 can be canceled to a certain extent by once writing onto the storage device 26 the data read from the disc 19.
The disc 19 may be a CD-ROM or a DVD-ROM each of which has a large data recording capacity. In order that data retrieving speeds may be improved, there has recently been a demand that the disc reproducing device reproduce data at higher speeds. As shown in FIG. 47, when data recorded on the disc 19 is reproduced at a high speed in a random manner, the pickup 20 is quickly moved to any track and thereafter, the disc 19 needs to be rotated at a constant linear speed. In this case, the pickup 20 can easily be moved quickly to the track. However, rotational inertia prevents the motor 30 from instantaneous response. Accordingly, the data reproducing speed varies until the rotational speed of the motor 30 reaches a constant linear speed. This results in a problem that data cannot be reproduced when the above-mentioned variations in the reproducing speed is not canceled in the storage device 26.
A motor with a high torque characteristic is considered to be used as the motor 30 for improvement in the responsibility. However, this increases an amount of current consumed by the servo circuit 23, presenting a definite limit. Further, in another arrangement, the disc is rotated in the CAV system for the purpose of reducing control burden of the motor 30. However, this arrangement cannot be applied to the device designed for use in the CLV system.
In view of the above-described problems, the prior art has proposed an improved system for a disc reproducing device for use with a computer, in which system the disc 19 is a CD-ROM, a DVD-ROM, etc. In this system, data is transmitted at the transmission side at a speed according to a data readout speed in a period of variations in the speed at which data is read out from the disc. Specifically, although the data readout speed needs to be set so as to usually maintain the CLV at a constant value according to a sampling rate of 44.1 KHz in the case of CD of the musical purposes, the above-mentioned use with the computer is free from such a limitation.
FIG. 48 shows an example of the improved system. In this system, clock signals supplied to the error correcting circuit 27 and the transmission circuit 28 are produced by frequency-dividing clock signals delivered from the system reference clock circuit 31 by a frequency divider circuit 32. A speed comparison circuit 33 monitors a write address of the storage device 26 for the decoding circuit 24, thereby changing a frequency-dividing ratio of the frequency divider circuit 32 according to a remaining recording capacity of the storage device 26. As a result, a speed at which the transmission data is read from the storage device 26 follows up a speed at which the received data is written onto the storage device 26.
In the above-described system, a frequency of the clock signals delivered from the system reference clock circuit 31 needs to be increased so that a reproducing speed or the speed at which the transmission data is read out is increased. This results in a problem of increases in unnecessary radio wave radiation causing malfunction of a microcomputer etc. and in consumed electric power.
FIG. 49 shows another prior art arrangement in which the clock signals supplied to the error correcting circuit 27 and the transmission circuit 28 are produced by frequency-dividing the clock signals the PLL circuit 22 produces based on the rows of received data.
According to this system, the variation in the reproducing speed is directly related with those in the operation clock signals of the error correcting circuit 27 and the transmission circuit 28. As a result, time base variations in the motor 30 need not be canceled via the storage device 26. However, in case where a rapid variation in the readout speed desynchronize the PLL circuit 22, there is a possibility that the frequency of the clock signals delivered therefrom may rapidly be increased. In this case, the clock signals supplied to the storage device 26, the error correcting circuit 27 or the transmission circuit 28 would exceed a respective limit operating speed, resulting in malfunction of the system.
FIG. 50 shows further another prior art arrangement in which the system reference clock circuit 31 delivers clock signals to the error correcting circuit 27 and the transmission circuit 28, and a speed comparing circuit 35 compares a speed at which the decoding circuit 24 writes the received data onto the storage device 26 and a speed at which the transmission circuit 28 reads out the transmission data from the storage device 26, whereby an interval at which the transmission circuit 28 reads out the transmission data from the storage device 26 is changed according to the result of comparison.
In this arrangement, a speed at which the clock signals are supplied to the error correcting circuit 27 and the transmission circuit 28 is set so as to be higher than the speed at which the decoding circuit 24 writes the received data onto the storage device 26. Further, each of the error correction and transmission circuits 27 and 28 starts data processing when a predetermined amount of data (one block of error correcting code in the DVD system, for example) is stored in the storage device 26. Upon completion of the data processing, each of the circuits 27 and 28 interrupts the data processing until another predetermined amount of data is stored.
According to the above-described system, an upper limit of the data reproducing speed depends upon the frequency of the clock signals delivered from the system reference clock circuit 31. Accordingly, a frequency of the operating clocks of each of the error correction and transmission circuits 27 and 28 is constant such that the operation of each circuit is ensured. However, each circuit is usually operated at a high frequency. This results in a problem of increases in unnecessary radiation and consumed electric power.
Therefore, a primary object of the present invention is to provide an error correcting device in which the recording capacity of the storage device can be reduced without an excessive increase in the processing speeds of the error correction means and transmission means, for the purpose of overcoming the problems in the above-described first prior art.
A second object of the invention is to provide an error correcting device in which a false correction can be prevented even when the calculation of syndrome is not properly carried out due to disturbance of the data receiving state, for the purpose of overcoming the problems in the above-described second prior art.
A third object of the invention is to provide an error correcting device in which a data overwriting circuit is not required and the false correction can be prevented when unrenewed data remains in the storage device, for the purpose of overcoming the problems in the above-described third prior art.
A fourth object of the invention is to provide a data reproducing device in which increases in unnecessary radiation and consumed electric power can be restrained and a transmission speed of data whose error has been correct can follow the speed at which the storage device receives data, for the purpose of overcoming the fourth problems.
The present invention provides an error correcting device comprising a receiving circuit for receiving data composed as an error correcting code in a unit of block, an error correcting circuit detecting an error in the data based on the error correcting code received by the receiving circuit and correcting the error, and a storage device having two areas each having a storage capacity corresponding to at least one block of the data. In this error correcting device, the receiving circuit and the error correcting circuit alternately switch in use the two areas of the storage device between a receiving data area into which the data received by the data receiving circuit is written and as a corrected data area into which the correct data is written. The transmission circuit reads out the data stored in the corrected data area, transmitting the data. Further, the receiving circuit writes the received data at an address at which the transmission circuit has read out the data within a period of time when the transmission circuit reads out one block of data from the area of the storage device to transmit the data, thereby using said area as the received data area.
According to the above-described error correcting device, while the two areas of the storage device are switched alternately between the received data area and the corrected data area, the transmission circuit reads out the data sequentially from the area of the storage device which was previously a corrected data area to transmit the read data, whereas the receiving circuit writes the received data at the address at which the transmission circuit has read out the data, within the period of time during which the transmission circuit reads out and transmits one block of the corrected data. Accordingly, an independent transmission data area is not required. This clearly differs from the prior art. Moreover, the receiving circuit sequentially overwrites the received data onto the area of the data the transmission circuit having already been read out. Accordingly, operating speeds of the error correcting and transmission circuits need not be increased excessively relative to an operating speed of the receiving circuit.
The error correcting device is preferably provided with a function of setting a difference between an address of the storage device at which the transmission circuit reads out the data whose error has been corrected by the error correcting circuit and an address of the storage device at which the receiving circuit writes the received data so that the difference is smaller than an address corresponding to a capacity of one block of the error correcting code.
The error correcting circuit preferably detects and corrects the error in one block of data, a time required for writing the corrected data onto the corrected data area of the storage device is set so as to be shorter than a time required for the receiving circuit to write received one block of data onto the storage device, and when the error correcting circuit finishes writing onto the corrected data area one block of the corrected data, the transmission circuit reads out the corrected data from a first address of the corrected data area before the receiving circuit completes the writing of one block of data onto the received data area.
According to the above-described error correcting device, the address of the storage device at which the transmission circuit reads out the corrected data slightly precedes the address thereof at which the receiving circuit writes the received data. Accordingly, the storage device owns in common an area from which the transmission data is read out and an area into which the received data is written by the difference between the addresses, namely, the difference between a period of time during which the transmission data is read out and a period of time during which the received data is written.
The transmission circuit preferably reads out the corrected data from the previous corrected data area of the storage device at a speed higher than a maximum speed at which the receiving circuit writes the received data onto the storage device. Further, the error correcting device preferably further comprises a readout speed control circuit for controlling a data readout speed of the transmission circuit based on a speed at which the receiving circuit writes the received data onto the storage device.
The error correcting device preferably further comprises an interrupting circuit for comparing an address at which the transmission circuit reads out the corrected data from an area of the storage device which was a last corrected data area and an address at which the receiving device writes the received data onto the storage device. In this case, the interrupting circuit interrupts a writing operation of the receiving circuit onto the received data area when an interval between the addresses is below a predetermined value.
Further, the error correcting device preferably further comprises a data erasure judging circuit for comparing an address at which the transmission circuit reads out from the storage device the corrected data and an address at which the receiving circuit writes the received data onto the storage device, thereby judging that untransmitted data which is stored in the storage device and regarding which an error correcting process has been executed has been erased.
The invention also provides an error correcting device comprising a receiving circuit for receiving data composed as an error correcting code, a storage device for storing the data received by the receiving circuit, an error correcting circuit detecting an error in the data based on the error correcting code received by the receiving circuit and correcting the error, the error correcting circuit further writing the error-corrected data onto the storage device, a transmission circuit for reading out the error-corrected data from the storage device to transmit the same, a syndrome calculating circuit obtaining the data received by the receiving circuit to calculate a syndrome of the obtained data based on the error correcting code, the syndrome calculating circuit delivering the calculated syndrome to the error correcting circuit, and a syndrome judging circuit for judging validity of the syndrome calculated by the syndrome calculating circuit based on a received state of the data obtained from the receiving circuit for use in calculation of the syndrome.
According to the above-described error correcting device, the syndrome calculating circuit directly obtains the received data without via the storage device, previously calculating the syndrome of the data from the error correcting code. Accordingly, the error correcting circuit can start the error correction without reading out the received data from the storage device in a case where the error of the data is detected as the result of the calculation of the syndrome by the syndrome calculating circuit when a first correction of error is corrected regarding the received data. In this case, furthermore, the error correcting circuit can cause the syndrome judging circuit to judge the validity of the syndrome calculated by the syndrome calculating circuit.
The above-described error correcting device preferably further comprises a syndrome output switching circuit for switching between a case where the syndrome output switching circuit delivers to the error correcting circuit the syndrome with respect to which the error of the data is uncorrectable, when the syndrome judging circuit has delivered the invalidity signal, and a case where the syndrome output switching circuit delivers to the error correcting circuit the syndrome calculated by the syndrome calculating circuit otherwise. In this constitution, the syndrome output switching circuit delivers to the error correcting circuit the syndrome with respect to which the error cannot be corrected, when the correction of the error of the data cannot properly be performed with the syndrome calculated by the syndrome calculating circuit. Consequently, the error correcting circuit can be prevented from a false correction.
The error correcting circuit does not preferably perform the error correction for at least a row of the error correcting code of the data corresponding to the syndrome judged to be invalid, when the syndrome judging circuit has delivered the invalidity signal.
The invention further provides an error correcting device comprising a receiving circuit for receiving data composed as an error correcting code, a storage device onto which the data received by the receiving circuit is written, a judging circuit for judging whether data of a predetermined number of symbols required for error correction is received by the receiving circuit and properly written onto the storage device, a renewal position information generating circuit for generating information of a renewal position regarding a row of code of the data written onto the storage device, based on a judgment of the judging circuit, an error correcting circuit reading out the data stored in the storage device to detect an error of the data based on the error correcting code, the error correcting circuit correcting the error of the data regarding which the error has been detected and writing onto the storage device the data regarding which the error has been corrected, the error correcting circuit refraining from performing the error correction for at least a row of the error correcting code with respect to which the data has not been renewed on the basis of the renewal position information generated by the renewal position information generating circuit, and a transmission circuit reading out and transmitting the data written onto the storage device and regarding which the error correction has been performed.
According to the above-described error correcting device, for example, an unrenewed row of code remains in an area of the storage device onto which no data is written when a disturbance in the data receiving state of the receiving circuit interrupts data reception. In this case, however, the error correcting circuit refrains or does not perform the error correction for the code row regarding which the information data has not been renewed, based on the renewal position information. This can prevent a false detection and a false correction regarding the unrenewed data without provision of means for collapsing data having been transmitted on the storage device, differing from the prior art.
In the above-described constitution, the data is preferably composed as a plurality of sequences of error correcting codes. In this case, when the number of rows of any one sequence of error correcting codes of the data regarding which rows the error correction has been performed is larger than the number of correctable errors in the other sequences of error correcting codes, the error correcting circuit performs the error correction for the rows of error correcting codes the data of which in said other sequences of error correcting codes has not been renewed.
According to this constitution, even if the error correcting circuit executes the error correction for the unrenewed code row regardless of the renewal position information, the error correction is not actually performed since the number of rows of any one sequence of error correcting codes of the data is larger than the number of correctable errors in the other sequences of error correcting codes. At this time, false correction is prevented. Further, for example, when data correction is executed for said any one sequence of code row at many times and the correcting process is repeatedly executed for each sequence of code row at a plurality of times, there is a possibility that the correction may be performed for the unrenewed code rows in subsequent correcting processes. Consequently, the correctability of the unrenewed data can be improved.
The invention also provides a data reproducing device comprising a receiving circuit for receiving data read out from a recording medium and composed as an error correcting code, a storage device onto which the data received by the receiving circuit is written, a clock signal supplying circuit for supplying clock signals independent of clock signals for control of data reception, an error correcting circuit reading out the data stored in the storage device based on the clock signals supplied thereto from the clock signal supplying circuit and correcting an error in the data regarding which the error has been detected, based on the error correcting code, the error correcting circuit writing onto the storage device the data regarding which the error has been corrected, and a transmission circuit for reading out and transmitting the error-corrected data written onto the storage device, based on the clock signals supplied thereto from the clock signal supplying circuit.
According to the above-described data reproducing device, the error correcting circuit and the transmission circuit are supplied with frequency-variable clock signals from the clock signal supplying circuit dedicated to both of them. Upon completion of the error correction for the data written onto the storage device by the receiving circuit, the error correcting circuit interrupts the error correction until the receiving circuit writes new data onto the storage device. When completing transmission of the data regarding which the error correcting circuit has corrected the error, the transmission circuit interrupts the transmission until the new data regarding which the error correcting circuit has corrected the error.
More specifically, by setting the frequency of the clock signals delivered from the clock signal supplying circuit, the error correction and transmission of the data by the error correcting circuit and the transmission circuit respectively can be performed at respective higher speeds than the data reception by the receiving circuit. Accordingly, the frequency of the system reference clock signals set at a large value need not be supplied to error correcting circuit and the transmission circuit for increase in the data reproducing speed, or clock signals a PLL circuit or the like generates from the received data need not be supplied to the error correcting circuit and the transmission circuit. Consequently, increases in consumed electric power and unnecessary radiation can be prevented, and occurrence of malfunction can be prevented.
The clock signal supplying circuit preferably includes a frequency control circuit for controlling a frequency of the clock signals in a feedback manner so that the frequency of the clock signals delivered from the clock signal supplying circuit approximates to a value set by the frequency setting circuit Further, the data reproducing device preferably further comprises a system control circuit for generally controlling a system and for setting a set value at the frequency setting circuit. When the recording medium is an information storage disc, the system control circuit changes an upper limit value of a data reproducing speed by setting the set value of the frequency setting circuit according to a type of the information storage disc storing the data to be reproduced. Further, the system control circuit changes an upper limit value of a data reproducing speed by setting the set value of the frequency setting circuit according to a position of a data reading element reading the data from the information storage disc.